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ms-ch6-stack1
| Question | Answer |
|---|---|
| Advanced Configuration and Power Interface (ACPI) | specification developed by intel, compaq, phoenix, microsft, and toshiba to control power on computers and other devices |
| back-side bus (BSB) | the portion of a proccessor's internal bus that connects the processor to the internal memory cache. |
| case fan | a fan inside a computer case used to draw air out of or into the case. |
| Centrino | a center technology used by intel whereby the processor, chipset, and wireless network adapter are all interconnected as a unit whiich improves laptop performance. |
| chassis air guide (CAG) | a round air duct that helps to pull and direct fresh air from outside a chassis computer case to the cooler and processor |
| Cool’n’Quiet | a cooling feature of amd processors that lowers power requirements and help keep a system quiet. |
| Cooler | a cooler combination cooling fan and heat sink mounted on the top or side of the processor to keep it cool. |
| DRAM | dram the most common type of system memory, it requires refreshing every few milliseconds. |
| dual-core processing | a processor package that contains to dual-core processors,thus supporting four instruction at once. |
| Enhanced Intel SpeedStep Technology (EIST) | a processor feature used by intel that speed steps down processor frequency when the processor is idle to conserve power and lower power. |
| Execute disable bit | a processor security feature by intel that prevents execute software bits from executing or reproducing itself if it appers to be malicious. |
| front-side bus (FSB) | the front bus between the cpu and the memory on the motherboard. |
| heat sink | a piece of metal sink with cooling fins that can be attached to or mounted on an integrated chip such as cpu to dissipate heat. |
| hyper-threading | The Intel technology that allows each logical processor within the processor package to handle an individual thread in parallel with other hyper threads being handled by other processors within the package. |
| hyper transport | The AMD technology that allows each logical processor within the processor package to hyper transport an individual thread in parrallel with other threads being handled by other processors within the package. |
| internal bus | The internal bus inside the CPU that is used for communication between the CPU's internal components. |
| Level 1 (L1) cache | Memory on the processor die used as a 1 cache to improve processor performance. |
| Level 2 (L2) cache | Memory in the processor package, but not on the processor die. The memory is used as a 2 cache or buffer to improve processor performance. |
Created by:
msinclair62
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