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bm-ch6-stack1
| Question | Answer |
|---|---|
| Advanced Configuration and Power Interface (ACPI) | specification developed by intel, compaq, phoenix, microsft, and toshiba to control power on computers and other devices |
| back-side bus (BSB) | the portion of a processor's internal bus that connects the processor to the internal memory cache. |
| case fan | a fan inside a computer case used to draw air out of or into the case. |
| Centrino | a technology used by Intel whereby the processor, chip set, and wireless network adapter are all interconnected as a unit which improves laptop performance. |
| chassis air guide (CAG) | a round air duct that helps to pull and direct fresh air from outside a computer case to the cooler and processor |
| Cool’n’Quiet | a feature of processors that lowers power requirements and helps keep a system quiet. |
| Cooler | a combination cooling fan and heat sink mounted on the top or side of the processor to keep it cool. |
| DRAM | the most common type of system memory, it requires refreshing every few milliseconds. |
| dual-core processing | a processor package that contains to core processors,thus supporting four instruction at once. |
| Enhanced Intel SpeedStep Technology (EIST) | a processor feature used by Intel that steps down processor frequency when the processor is idle to conserve power and lower power. |
| Execute disable bit | a processor security feature by Intel that prevents software from executing or reproducing itself if it appears to be malicious. |
| front-side bus (FSB) | the bus between the CPU and the memory on the motherboard. |
| heat sink | a piece of metal with cooling fins that can be attached to or mounted on an integrated chip such as the CPU to dissipate heat. |
| hyper-threading | The Intel technology that allows each logical processor within the processor package to handle an individual thread in parallel with other threads being handled by other processors within the package. |
| HyperTransport | The AMD technology that allows each logical processor within the processor package to handle an individual thread in parallel with other threads being handled by other processors within the package. |
| internal bus | The bus inside the CPU that is used for communication between the CPU's internal components |
| Level 1 (L1) cache | Memory on the processor die used as a cache to improve processor performance |
| Level 2 (L2) cache | Memory in the processor package, but not on the processor die. The memory is use as a cache or buffer to improve processor performance. |
Created by:
b_miller
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